Rajesh Pawar

Full chip interrupts verification

• Developed and executed test cases to verify interrupt functionality across multiple IP blocks in ARM-based SoCs.
• Validated end-to-end interrupt workflows, including hardware generation, GIC routing, and software servicing, ensuring robust hardware-software integration.

Block-level verification of Temperature Sensor Controller

• Led block-level verification of the temperature sensor controller, including test planning, SystemVerilog/UVM-based testbench development, and creation of reusable verification components.
• Executed a comprehensive suite of directed and constrained-random tests to validate sensor data acquisition, threshold detection, and register interface behavior under various thermal scenarios, achieving full functional and code coverage.

Full-chip PCIe verification

• Executed full-chip PCIe verification, including the initialization and bring-up of PCIe links.
• Conducted end-to-end testing of data paths from the ARM CPU core through PCIe interfaces, using loopback tests.

Full-chip Bootflow verification

• Created and executed verification tests to validate the complete boot sequence, including BootROM and BL1 loading, ensuring seamless progression through early boot stages.
• Simulated diverse boot scenarios to catch corner cases and verify system resilience during initialization.
• Collaborated closely with firmware and hardware design teams to align verification efforts with architectural specifications and design intent.

• Created board to bring up utilities for the HAPS-80D prototyping platform.
• Developed scripts to perform hardware checks on DDR4, SPI flash memory.
• Involved in debugging SOC design partitioning issues on the prototyping platform.