Yassine Fadel

Unit Level Verification :

• Run the Superlint and Autoformal check on the block
• Collaborate with the designer, analyze design specification and extract verification requirement
• Prepare a test plan and test-bench environment.
• Integrate C Reference models into the testbench.
• Developed checkers and assertion checks.
• Debug failures and report the bugs to the designer.
• Created a functional coverage collector.
• Run regression and collect verification metrics, update the verification plan.
• Understand and analyze RTL code coverage results and functional coverage methods.
• Successful verification closure for the block.

SoC Level Verification :

• Reused the tests that I developed at unit level at the Soc level for the block
• Helped in maintaining the verification environment for the SoC level.
• Modify Perl/Bash/Python/Ruby scripts
• Worked as Team member Tasks are assigned on individual/Team bases & successfully completed throughout the project.
• Debug, report, and work closely with design engineers.
• Integrate C/C++/Matlab Reference models into the testbench.
• Debug test failures to determine if it is a design or verification issue; work with the design team to correct defects and test issues.
• Worked on functional safety (FuSa) mechanisms verification at th SoC level: Error Injection.

HDL Language : Verilog, SystemVerilog, VHDL HVL : System Verilog

EDA Tools : Xcelium, Simvision, IMC, Vmanager. EDA Scripting : Tcl, Python, ScriptShel, Ruby. HVL Methodology : UVM, Directed Testing

VLSI Version Control : SVN

• ASIC Design Verification

Duration 6 Months

Contributions: Worked as a verification trainee and successfully completed the tasks assigned to me.

• Attended training courses to build my understanding of processes, techniques, and industry: SystemVerilog, UVM, Cadence Tooling, Scripting
• Verified functionalities at the top level and developed test-cases.
• Written directed tests in C and constrained random tests with systemverilog and UVM.
• Prepared a verification plan for unit level verification for an IP.

Tools: Cadence Design Tooling( Xcelium, Simvision), Jira, SVN

Languages: System Verilog, C.